Phase 1.2 of the project: Code is ready, now auto-generated layout from it.. I used Encounter TM + TCL scripts for the same.
I used the scripts given by my TA, links: www.cs.utah.edu/~elb/cadbook/Chapters/AppendixB/
some tutorials about encounter: http://www.et5.tu-harburg.de/Studium/Praktikum/Cadence_digital/Scripte/4%20-%20Layout.pdf
Getting Pins in the order you want: since my project used data buses, I absolutely wanted the pins in a particular order. Though I am not a pro at it yet.. I used Pin Editor in Encounter (Thanks Aswin :) ).. way easier than writing a TCL EditPin command per pin.
1) After you run your TCL script in Encounter.. type win to see the layout
2) In the layout window go to Edit --> Pin Editor, define the pin locations, (right/ left..offset between pins)
3) go to file/Save/IO Editor - save as $designName.save.io
4) include this in your TCL script - loadIoFile "$designName.save.io" and run Encounter again.
Just for the sake of comparison.. the TCL command for the short, sweet n fast steps mentioned above would be:
editPin -cell name_of_your_cell -pin {name_of_your_pin} -spreadType RANGE -edge 2 -layer Metal3 -use Clock -fixOverlap 1 -snap TRACK -pinDepth 10 -start {600 200} -end {600 400} -spacing 2 -unit TRACK -fixedPin 1
These tips from my friend Aswin made the task faster..and this was something Google hadnt told me.. I guess in Digital Designing you learn most tricks of the trade with experience.
Phase 1.3: Pad Design for the FSM + FIFO module
We had Pad designing for extra credit last semester, so very few groups did it. I turned to good old google for other Universities' AVLSI project guidelines + Aswin walked through the process on Gtalk.
Step 0: Importing Pads library into cadence
http://plaza.ufl.edu/cmcglone/eel5322/faqs.htm#q4
http://www.mosis.com//cell-libraries/scn025-pads-tiny
http://ecee.colorado.edu/~ecen5837/cadence/Adding_IO.html
http://www.eng.umd.edu/~dilli/research/layout/cadencetutorial/cadencedemo8.html
1. Pad frame
This is to get an idea of the number of "extra" or Padnoconnect cells required.
I simply edited the sample pad frame provided by MOSIS PADS library called the mini_frame.
2. Actual laying out of pads:
We simply need to rotate the pad layout according to our pad frame orientation, copy this rotated version, and paste in our layout. We need to align the pads side-by-side to form a complete rectangle/ square. Hence before we start with the actual layout, we should do a pad_frame.
3.Making connections
I guess getting an advanced degree primarily helps you to learn by yourself, the feeling when you dint know something and when you figure it out on your own.. priceless!!
Other good resources:
http://www.ee.ucla.edu/~dejan/ee115c/ee115c_tut_4.htm
standard cadence tutorial: http://www.ece.virginia.edu/~mrs8n/cadence/tutorial2.html
I used the scripts given by my TA, links: www.cs.utah.edu/~elb/cadbook/Chapters/AppendixB/
some tutorials about encounter: http://www.et5.tu-harburg.de/Studium/Praktikum/Cadence_digital/Scripte/4%20-%20Layout.pdf
Getting Pins in the order you want: since my project used data buses, I absolutely wanted the pins in a particular order. Though I am not a pro at it yet.. I used Pin Editor in Encounter (Thanks Aswin :) ).. way easier than writing a TCL EditPin command per pin.
1) After you run your TCL script in Encounter.. type win to see the layout
2) In the layout window go to Edit --> Pin Editor, define the pin locations, (right/ left..offset between pins)
3) go to file/Save/IO Editor - save as $designName.save.io
4) include this in your TCL script - loadIoFile "$designName.save.io" and run Encounter again.
Just for the sake of comparison.. the TCL command for the short, sweet n fast steps mentioned above would be:
editPin -cell name_of_your_cell -pin {name_of_your_pin} -spreadType RANGE -edge 2 -layer Metal3 -use Clock -fixOverlap 1 -snap TRACK -pinDepth 10 -start {600 200} -end {600 400} -spacing 2 -unit TRACK -fixedPin 1
These tips from my friend Aswin made the task faster..and this was something Google hadnt told me.. I guess in Digital Designing you learn most tricks of the trade with experience.
Phase 1.3: Pad Design for the FSM + FIFO module
We had Pad designing for extra credit last semester, so very few groups did it. I turned to good old google for other Universities' AVLSI project guidelines + Aswin walked through the process on Gtalk.
Step 0: Importing Pads library into cadence
http://plaza.ufl.edu/cmcglone/eel5322/faqs.htm#q4
http://www.mosis.com//cell-libraries/scn025-pads-tiny
http://ecee.colorado.edu/~ecen5837/cadence/Adding_IO.html
http://www.eng.umd.edu/~dilli/research/layout/cadencetutorial/cadencedemo8.html
1. Pad frame
This is to get an idea of the number of "extra" or Padnoconnect cells required.
I simply edited the sample pad frame provided by MOSIS PADS library called the mini_frame.
2. Actual laying out of pads:
We simply need to rotate the pad layout according to our pad frame orientation, copy this rotated version, and paste in our layout. We need to align the pads side-by-side to form a complete rectangle/ square. Hence before we start with the actual layout, we should do a pad_frame.
3.Making connections
Since I was using pad design for a module in a microprocessor, I used bidirectional IO pads. Each i/o pad is a bidirectional buffer with an input, an
output and an output enable. To use a I/O pad as input-only, enable = 0, to use as output-only enable = Vdd.
Ground and IO pads can be kept at the centre of top/ bottom rows. I guess getting an advanced degree primarily helps you to learn by yourself, the feeling when you dint know something and when you figure it out on your own.. priceless!!
Other good resources:
http://www.ee.ucla.edu/~dejan/ee115c/ee115c_tut_4.htm
standard cadence tutorial: http://www.ece.virginia.edu/~mrs8n/cadence/tutorial2.html
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