Phase 2 of the project: Delay Locked Loop design
Components: Phase Detector
Digitally Controlled Delay Line (controlled by a counter)
Components of DCDL:
Delay element
Mux
I used Buffer (Inverter driving inverter) as delay element. The delay line is made up of increasing delay. Hence I used Buffers with inverters of sizes 1, 2, 4.. and so on. To obtain these binary-weighted sized inverters, i used inverters in parallel, in layout as well as in schematic.
I got errors in LVS. In my 1 and 1/2 year dabbling with Cadence, this was the 1st time I got a LVS mismatch. So, initially I was clueless about debugging. My friends Akshay and Usri rushed to help. Akshay advised that I should repeat the layout, and I should verify LVS for each small block. I compared the netlists generated from schematic to the netlist after extraction. The errors were in the Mux. My initial design: All PMOS's shared the same P-Active region. Hence, they were getting shorted to Vdd. This was detected from checking the Extracted circuit. When you use "mark nets" in Extracted view, it doesnt help much. But when you right click on a particular thing in the Extracted view, everything that is electrically connected to it is highlighted. This is how I figured out that the metals were getting shorted. Solution: I used 2 separate P-active regions.
The Final compact layout:
The other errors were because I forgot to "Create path" for M2_M1 as well as M1_poly when I was connecting M2 to poly. These errors were more difficult to figure out, solved by observation. Hadn't I done my background net surfing? Sure! I did. But I dint find any mux layout on the net. Maybe I need to come up with better keywords. But in a way, I am glad I made that mistake--Its the process of learning from your mistakes that's important. I learnt a few new techniques of debugging layouts.\m/
Note: Mux is still crappy. Adding tremendous delay to my circuit. A possible solution is to keep the slowest inputs/ those that arrive last, closest to the output.
Components: Phase Detector
Digitally Controlled Delay Line (controlled by a counter)
Components of DCDL:
Delay element
Mux
I used Buffer (Inverter driving inverter) as delay element. The delay line is made up of increasing delay. Hence I used Buffers with inverters of sizes 1, 2, 4.. and so on. To obtain these binary-weighted sized inverters, i used inverters in parallel, in layout as well as in schematic.
I got errors in LVS. In my 1 and 1/2 year dabbling with Cadence, this was the 1st time I got a LVS mismatch. So, initially I was clueless about debugging. My friends Akshay and Usri rushed to help. Akshay advised that I should repeat the layout, and I should verify LVS for each small block. I compared the netlists generated from schematic to the netlist after extraction. The errors were in the Mux. My initial design: All PMOS's shared the same P-Active region. Hence, they were getting shorted to Vdd. This was detected from checking the Extracted circuit. When you use "mark nets" in Extracted view, it doesnt help much. But when you right click on a particular thing in the Extracted view, everything that is electrically connected to it is highlighted. This is how I figured out that the metals were getting shorted. Solution: I used 2 separate P-active regions.
The other errors were because I forgot to "Create path" for M2_M1 as well as M1_poly when I was connecting M2 to poly. These errors were more difficult to figure out, solved by observation. Hadn't I done my background net surfing? Sure! I did. But I dint find any mux layout on the net. Maybe I need to come up with better keywords. But in a way, I am glad I made that mistake--Its the process of learning from your mistakes that's important. I learnt a few new techniques of debugging layouts.\m/
Note: Mux is still crappy. Adding tremendous delay to my circuit. A possible solution is to keep the slowest inputs/ those that arrive last, closest to the output.
Some resources for LVS verification tips:
ReplyDeletehttp://www.seas.upenn.edu/~ese570/manual_17.htm