Digital Design Practice - 3

So I was asked about sizing of NAND gates. I gave the regular textbook answer of PMOS = size 2, NMOS = 2. Then I was asked if I could use other sizes. I said yes I could downsize what I want faster and upsize the other to keep total resistance the same.
For instance I can choose NMOS sizes as 4R/3 and 4R. The gate with size 4R/3 will be much faster.

There's a small derivation for calculating gate size for least average delay. Here it goes:
For inverter driving other inverter
For NMOS: assume size X, assume PMOS is Y times as big as NMOS. so PMOS size is YX.
NMOS resi = R/X, cap = XC
PMOS resi = 2R/XY, cap=XYC
falling delay = R/X(XC + XC + XYC + XYC) = 2(1+Y)RC
rising delay = 4(1+Y)RC/Y
2 * t-average = 2RC (3+ Y + 2/Y)
to get minimum t-average we have to find derivative w.r.t Y
1-2/Ysquare = 0
Y = root-2

unit width transistor = 6 lambda (contact size 2, surrounded by 1 diffusion for diff-contact connection, surrounded by 1 lambda because if you want to have twice unit width and all, there is minimum spacing you need between 2 metals.) For unit average resistance:
6R/X + 12 R/root2*X = 2R
X = 3*root2 + 3 = 7.24 lambda

So for least average delay, inverter sizing is NMOS = 7.24 lambda, PMOS = root2 * 7.24 lambda = 10.24 lambda.

I was curious if this root2 sizing holds good for other gates too? and also for different driver-load combinations?
Lets choose a inverter driving NAND.
2 inputs of NAND are shorted together driven by INv, so its gate cap at inverter load = 2XC + 2XYC.
2* t-average = R/X ( XC + XYC + 2XC + 2XYC) + 2RC/XY (3XC + 3XYC)
2* t-average = 3RC (1+Y + 2/Y + 2)
2*t-average = 3RC(3 + Y + 2/Y)
Surprise surprise!! the root2 sizing holds good for this case too!!
So basically this Y + 2/Y part that contributes to derivative is coming from the mobility ratio which I assumed as 2.
So in general if NMOS mobility is n times PMOS mobility, for least average delay the PMOS is root-p times NMOS.

Case 2: Least sizing for NAND2
Temporarily taking X out of equation.
NMOS size = 2, PMOS size = Y
Assume NAND driving inverter.
Bottommost nmos sees:  2C + 2C + YC + YC + YC + C capacitance on its path to Y.
upper nmos sees:  3C + 3YC cap.
elmore delay when nmos on: RC/2(5+3Y+3+3Y) = RC(4+3Y)
each pmos sees: YC + YC + 2C + YC + C
elmore delay when one of the pmos on = 2RC/Y(3Y + 3)
2*t-average = RC(4+3Y + 6 + 6/Y)
3 -6/Ysquare = 0
Y = root2
PMOS size = root2, NMOS =2

Sometimes, elmore delay is also calculated in terms of how much resi. a capacitor sees. Same thing effectively.
rising delay when only 1 pmos on: 2R/Y( 3C+3YC) = RC(6/Y + 6)
falling delay when both nmos on: R/2*2C + R*(3C+3YC) = RC (4 + 3Y)

Case 3: Least sizing for NOR2 driving inverter
NMOS size = 1, PMOS size = 2Y
Topmost pmos sees: (2Y + 2Y + 2 + Y + 1)C = (5Y + 3)C
lower pmos sees: (3Y + 3)C
elmore delay when both pmos on: 2RC/2Y*(5Y+3) + 2RC/2Y*(3Y+3)  = RC(8+6/Y)
each nmos sees: (3+ 3Y)C
elmore delay when one of the nmos is on: RC(3+3Y)
2*t-average = RC(8 + 6/Y + 3 + 3Y)
-6/Ysquare+3 = 0
Y = root2
PMOS size = 2root2, NMOS size=1

It is quite impressive that Y came out to be root2 for gates when inverter was considered as the load.

Case 4: NOR3 driving F*NOR3
NMOS size=1, PMOS size = 3Y
pmos on: 2RC/3Y(9Y + 3 + 9FY + 3F) + 2RC/3Y(6Y+3 + 9FY + 3F) + 2RC/3Y(3Y+3 + 9FY +3F) =2RC/3Y(18Y +9+27FY + 9F)
=RC/(12+6/Y+18F+6F/Y)
one of the nmos on: RC(3Y+3 + 9FY + 3F)
2*t-average = RC(12 + 6/Y + 18F + 6F/Y + 3Y + 3 + 9FY + 3F)
 -(6F+6)/Ysquare + (3+9F) =0
Y=root {(6F+6)/(9F+3)}