Digital Design practice - 4

Assume Cload on an EXOR-2 gate = 108 units. (yup I purposely chose it so that stage gain will be a whole number)
Approach one: every stage has equal gain
3 stage NAND realization of EXOR-2: stage 1: Y1= A NAND B
               stage 2: 2 branches, B1= Y1 NAND A, B2= Y1 NAND B
               stage 3: out = B1 NAND B2
Logical effort of 2 input NAND = 4/3.
L.E of path = 4/3 * 2 * 4/3 * 4/3
Gain of path = Cload/ Cin * path LE = 108 * 128/27 = 4 * 2 * 4 cubed
stage gain = Nth root of path gain, where N = number of stages, aka 3 in our example.
stage gain  = 8
(Note: Optimum gain is 4, though gain of 2-6 is also OK. Probably in this case we need to use a 4th stage?)
Working gate sizes backwards: gain = LE * Cout / Cin
Cin = LE * Cout / gain
Cin3 = 4/3 * 108/ 8 = 18
Cin2 = 4/3 * 18 / 8 = 3

since there were 2 branches at stage 2, Cout1 = 2*3=6
Cin3 = 4/3 * 6/ 8 = 1 (getting Cin =1 confirms that calculations are correct)

Now, get the gate sizes: suppose unit gate capacitance corresponds to 20 lambda
stage1: PMOS 2, NMOS 2 => PMOS or NMOS W/L is 10lambda/2 lambda
stage2: PMOS 6, NMOS 6 => W/L is 30lambda/2lambda
stage3: PMOS 36, NMOS 36 => W/L is 180lambda/2lambda

delay of nand2: falling: R/2*2C + R*(6C+4fC) = RC( 4f + 7)
rising: R*(4f+8)
average delay = 4f + 7.5

stage1 f=3*2=6, stage2 f=6, stage3 f= 6
delay of the exor gate designed above = 3*(4*6 + 7.5) = 94.5


Another way to solve this is such that every stage has equal fanout.  The 3rd technique to solve this is such that every stage has equal delay. In this case all 3 methods give same answer because all 3 stages are the same.
I will pick a different value of Cload for some extra practice.
Let Cload = 81.
Method2: equal fanout: F = cuberoot (81*2) = 5.45;
Cin2 = 5.45 * Cin1 /2 = 2.725
Cin3 = 2.725 * 5.45 = 14.85
Cload= 14.85 * 5.45 = 81 confirmed, and verified calculations.
delay = 3 (4f + 7.5)  = 3(4*5.45 + 7.5) = 87.9
Equal fanout method is very convenient to do quick mental calculations.
gate sizes: stage1: PMOS, NMOS W/L = 10 lambda/2 lambda
stage2: PMOS, NMOS W/L = 27.256 lambda/ 2lambda
stage3: PMOS, NMOS W/L= 148.586 lambda

I will pick a different combination for more practice. Lets do an OR gate with Cload = 15.
Method1: equal stage gain
NOR-2 g= 5/3, INV g=1, path LE 5/3 * 1 = 5/3
path gain = path LE * Cout / Cin = 5/3*15=25
stage gain = root (25) = 5
Cout/Cin * stage_LE = stage_gain
Cin = LE * Cout / stage_gain
Cin for inverter = 1 * 15/ 5 = 3.
Gtae sizing assuming unit capacitance = gate capacitance for 20 lambda
NOR-2: PMOS=16/2, NMOS =4/2
INV: PMOS = 40/2, NMOS = 20/2
delay of NOR2: rising: 2R/4*4C + 2R/2(4C + 4C + 2C + 5hC) = RC (12 + 5h)
falling: R(4C + 2C + 5h) = RC(6+5h)
average = RC(5h + 9)
stage1 f = 3/1 = 3, stage2 f = 15/3 = 5
delay = (5*3 + 9) + (3*5 + 3) = 42

Method2: equal fanout, f = root(15) = 3.87
Gate sizing:
NOR-2: PMOS 16/2, NMOS = 4/2
Cin2 = 3.87= 77.4 lambda cap, INV: PMOS=51.6/2, NMOS=25.8/2 => obviously we have to choose whole number sizing, PMOS = 52/2, NMOS=26/2
delay = 8*3.87 + 12 = 42.96

Method3: equal stage delay:
5h1+9=3h2+3, where h1h2=15
h2=(5h1+6)/3
h1*(5h1+6)=45
5h1square + 6h1 -45 =0,
roots = {-6 +/- root (36+4*5*45)}/10
h1= 2.46
delay = 2( 5*2.46 + 9) = 42.6
Note that all the 3 methods give very close results.
Also note that delay is least when using equal stage_gain.

Just for comparison, lets do OR using INV followed by NAND-2.
path LE = 1 * 4/3 = 4/3
path gain = 20
stage gain = root(20)=4.47
Cin2= 4/3*15/4.47=4.47
stage f2= 15/4.47 = 3.35, f1=4.47
delay = (3*4.47 + 3) * (4/3 * 3.35 + 9) = 30
Wow, the INV-NAND2 or gate is so much faster than NOR2-INV or gate.