Digital design practice

1. Sequence detector:
Easiest option for a small sequence is to use one hot encoding.
Example: circuit to detect the sequence 1001.
Just save past 4 input history aka 4 flip flops.
Output = Q.Q-1bar.Q-2bar.Q-3

Just putting up my practice encoding (non-one-hot):

2. Sequence Generator:
Simplest option is a bunch of flip flops arranged as shift registers, parallel load, shift out serially. The advantage of this approach is that new sequence is just as easy as the next set of data loaded in.
The way to generate same sequence over and over is to have a bunch of flip flops, again arranged as shift registers, but now the input data is determined by the "state" of flip flops.
The minimum number of flip flops needed depends upon the number of flip flops needed to get a unique state.
For instance lets get a simple sequence generator for sequence, 101001, 1st lets try with minimum = 3 flip flops, and check if all states are unique. In this case, they are unique with just 3 FFs.

3. Divide by 3 counter with equal duty cycle
The equal duty cycle is the catch here, and we have to use both positive and negative edge triggered flip flops.
My spur of the moment answer used 2 mod-3 counters, one on +ve edge and one on -ve edge, i anded their Q1bars to get divide-by-3-with-equal-duty-cycle.
The elegant solution is inspired by R.P.Jain, example 8.4.
It is a mod-3-counter, the output of which is fed to -ve edge triggered flipflop. With some output jugglery, we get required divide-by-3-with-equal-duty-cycle output.

4. Timing Analysis:
Data should be stable setup_time before clock edge and hold_time after clock edge.
Hence maximum [clock-to-q + combinational delay] (ignoring skew) < clock period - setup time
minimum [clock-to-q + combinational delay] > hold_time

Also note that hold_time + setup_time should be less than clock_period, else reduce the clock_frequency.
Solving Setup time violation
1. Reduce clock speed
2. Increase drive strength
Suppose initially a unit sized inverter is driving another unit inverter which drives a large load, lets call it Clarge.
delay = R(6C) + R(3C + Clarge)
Now lets add drive strength to inverter2 by using wider transistor => resistance goes down
delay = R(9C) + R/2(6C + Clarge)
3. Adding buffer to clock path, this effectively adds buffer_delay_time to hold_time and might cause hold violation.

Solving hold violation
1. Insert buffers in data path to increase minimum combinational delay.
2. If you discover a hold time violation after the chip is in silicon, do you just chuck out the chip? One of my interviewers told me this: just lower the Vdd. :)

5. Charged capacitor in parallel to uncharged capacitor
2 things happen here, a. charge is conserved, and b. voltage across the 2 capacitors must be same because they are in parallel.
Consider initial case: capacitor C1, charged to voltage V0. charge on capacitor = C1V0
When the capacitor is connected to uncharged capacitor, charge sharing takes place instantly.
Let V be common parallel combination voltage.
C1V0 = C1 V + C2 V
V = C1 /(C1+C2) * V0
The cool thing about this is what happens to the energy. Initial energy = 1/2C1V0^2, final energy = 1/2 (C1V0)^2 / C1+C2.
The difference in these 2 numbers is the energy spent in sending that charge from cap1 to cap2.

Charge sharing is an issue for dynamc logic. Lets consider a dynamic NAND gate, with NMOS for input A as inner input (drain connected to output bus). If input A = 1, and B=0 during evaluation phase, the expected output is 1. But because the uncharged parasitic capacitor on A is now in parallel with charged output capacitor, the actual output is (Cadiff/ Cadiff + Cload) * Vdd.  We need to use a weak pull-up PMOS to counteract this issue.