Digital Design practice - 5

1. Mod-3 counter without using reset
Excitation table:
0 0 -> 0 1
0 1      1 0
1 0      0 0
1 1      0 0
D1= D1bar.D0
D0=D0bar.D1
If spuriously there is a 11 (say on turning on) it will be cleared because NS is assigned 00.

2. 1-wire communication to power the slave chip in addition to communication.

data output goes 2V to 1.5V, Vout = 1.5 V

3. 
Gate delay : What is so magical about FO4, and other stuff
Say we have to drive a load = 256 * inverter cap   (textbooks usually choose 64 for discussion, but 256 has a whole number squareroot, cuberoot, and fourth root. )
I calculated delay for following:
1. size one inverter driving this FO-128 load
2. size one inverter -> driving a larger inverter -> driving the FO-128 load
3..and so on.

N stages		Delay calculation	Simplified delay
1	Size 1 inverter	RC*(3*128 + 3)	3RC(128+1)
2	Size of stage 2 inverter = root256 = 16	3RC(16 + 1) + 3RC/16 * (256+ 16)	3RC(8root2+1) + 3RC(8root2 + 1) = 2 * 3RC(8root2 + 1)
3	Size of stage 2 inverter = cuberoot256 Size of stage 3 inverter = square of cuberoot256	3RC(cuberoot128 + 1) + 3RC/cuberoot128(square_of_cuberoot128 + cuberoot128) + 3RC/square_of_cuberoot128(128 + square_of_cuberoot128)	3RC(cuberoot128 + 1) + 3RC (cuberoot128 + 1) + 3RC (cuberoot128+1) = 3 * 3RC (cuberoot128 + 1)

From above calculation, we can reach a general equation
For N stages of increasing sized inverters:
Each inveryer is Nth-root-of-Cload times bigger than the previous.
Each stage delay = 3RC ( Nth root of Cload + 1)
Total delay for N stages = N * 3RC (Nth root of Cload + 1)
ln (total delay ) = ln (3RC) + ln N + 1/N * ln Cload
Taking the usual stuff about minimum delay => derivative of this = 0 at what value of N