Empty Mind

Start of vacation.. nothing major to do..
attending (what would have been mine) Graduation..day full of shopping, running down the slope to catch a bus with shop-weary feet and hands full of A&F cardboard bags which obstruct running..
movies.. online chess.. mindless getting accosted by random males on the online chess site..
organizing a mini-party..
booking tickets for a Christmas-to-New Year vacation.. something to look forward to..
catching up with friends.. helping them shop/ pack.. feeling guilty when other batchmates get to meet their parents and you cant..
writing a letter to be sent back home with Pune-bound friends..sending your best photo from Gator Nights and the Commencement ceremony booklet back home..
waiting for the grades..
Online chess.. again.. and again.. and again.. because there is nothing better to do..
Empty mind is a..chess workshop :)

Pin Editing + Pad Design in Cadence

Phase 1.2 of the project: Code is ready, now auto-generated layout from it.. I used Encounter TM + TCL scripts for the same.
I used the scripts given by my TA, links: www.cs.utah.edu/~elb/cadbook/Chapters/AppendixB/
some tutorials about encounter: http://www.et5.tu-harburg.de/Studium/Praktikum/Cadence_digital/Scripte/4%20-%20Layout.pdf
Getting Pins in the order you want: since my project used data buses, I absolutely wanted the pins in a particular order. Though I am not a pro at it yet.. I used Pin Editor in Encounter (Thanks Aswin :) ).. way easier than writing a TCL EditPin command per pin.
 1)  After you run your TCL script in Encounter.. type win to see the layout
 2)  In the layout window go to Edit --> Pin Editor, define the pin locations, (right/ left..offset between pins)
 3)  go to file/Save/IO Editor - save as $designName.save.io
 4)  include this in your TCL script - loadIoFile "$designName.save.io" and run Encounter again. 

Just for the sake of comparison.. the TCL command for the short, sweet n fast steps mentioned above would be:
editPin -cell name_of_your_cell -pin {name_of_your_pin} -spreadType RANGE -edge 2 -layer Metal3 -use Clock -fixOverlap 1 -snap TRACK -pinDepth 10 -start {600 200} -end {600 400} -spacing 2 -unit TRACK -fixedPin 1 

These tips from my friend Aswin made the task faster..and this was something Google hadnt told me.. I guess in Digital Designing you learn most tricks of the trade with experience.

Phase 1.3: Pad Design for the FSM + FIFO module
We had Pad designing for extra credit last semester, so very few groups did it. I turned to good old google for other Universities' AVLSI project guidelines + Aswin walked through the process on Gtalk. 

Step 0: Importing Pads library into cadence
http://plaza.ufl.edu/cmcglone/eel5322/faqs.htm#q4
http://www.mosis.com//cell-libraries/scn025-pads-tiny
http://ecee.colorado.edu/~ecen5837/cadence/Adding_IO.html
http://www.eng.umd.edu/~dilli/research/layout/cadencetutorial/cadencedemo8.html

1. Pad frame
This is to get an idea of the number of "extra" or Padnoconnect cells required. 
I simply edited the sample pad frame provided by MOSIS PADS library called the mini_frame.

2. Actual laying out of pads:
We simply need to rotate the pad layout according to our pad frame orientation, copy this rotated version,  and paste in our layout. We need to align the pads side-by-side to form a complete rectangle/ square. Hence before we start with the actual layout, we should do a pad_frame.

3.Making connections

Since I was using pad design for a module in a microprocessor, I used bidirectional IO pads.  Each i/o pad is a bidirectional buffer with an input, an output and an output enable. To use a I/O pad as input-only, enable = 0,  to use as output-only enable = Vdd.

Ground and IO pads can be kept at the centre of top/ bottom rows. 

I guess getting an advanced degree primarily helps you to learn by yourself, the feeling when you dint know something and when you figure it out on your own.. priceless!!

Other good resources:
http://www.ee.ucla.edu/~dejan/ee115c/ee115c_tut_4.htm
standard cadence tutorial: http://www.ece.virginia.edu/~mrs8n/cadence/tutorial2.html

2:1 Restoring Inverting Mux Layout

Phase 2 of the project: Delay Locked Loop design
Components: Phase Detector
Digitally Controlled Delay Line (controlled by a counter)
Components of DCDL:
                                  Delay element
                                  Mux

I used Buffer (Inverter driving inverter) as delay element. The delay line is made up of increasing delay. Hence I used Buffers with inverters of sizes 1, 2, 4.. and so on. To obtain these binary-weighted sized inverters, i used inverters in parallel, in layout as well as in schematic.

I got errors in LVS. In my 1 and 1/2 year dabbling with Cadence, this was the 1st time I got a LVS mismatch. So, initially I was clueless about debugging. My friends Akshay and Usri rushed to help. Akshay advised that I should repeat the layout, and I should verify LVS for each small block. I compared the netlists generated from schematic to the netlist after extraction. The errors were in the Mux. My initial design: All PMOS's shared the same P-Active region. Hence, they were getting shorted to Vdd. This was detected from checking the Extracted circuit. When you use "mark nets" in Extracted view, it doesnt help much. But when you right click on a particular thing in the Extracted view, everything that is electrically connected to it is highlighted. This is how I figured out that the metals were getting shorted. Solution: I used 2 separate P-active regions.

The Final compact layout:

 

The other errors were because I forgot to "Create path" for M2_M1 as well as M1_poly when I was connecting M2 to poly. These errors were more difficult to figure out, solved by observation. Hadn't I done my background net surfing? Sure! I did. But I dint find any mux layout on the net. Maybe I need to come up with better keywords. But in a way, I am glad I made that mistake--Its the process of learning from your mistakes that's important. I learnt a few new techniques of debugging layouts.\m/
Note: Mux is still crappy. Adding tremendous delay to my circuit. A possible solution is to keep the slowest inputs/ those that arrive last, closest to the output.

The Iron Lady

Being citizens of the largest democracy in the world, we take so many things for granted. Assuming that democracy exists in itself is a joke, when the elected people rule over us as if they were aristocrats. Or, when we, the people, ourselves elect the progeny of so-called illustrious leaders, as if the right to "throne" comes by birth and not by qualifications.

The politics of forming a new state from a larger one is not new to us. My state faces this issue every now and then hoping that a new state made from the not-so-fertile area will fetch them more government grants. Most of my friends belong to another state, where people feel that the other part of the state is more tech-savvy, and hence they need to separate to ensure jobs for their kids. Both these regions are located in the central part of the nation. But it is a major security concern when tiny states dangerously close to 3 international borders demand separation. Especially when one of the 3 neighbours is a borderline bully, and wants to grab any land mass it sets its eyes upon.

Naturally, the government is super-scared, and has bestowed unlimited rights to the Army. But unfortunately, with power comes a huge responsibility, and not many people live up to it. With power, there soon creeps up a tendency to make people yield to the power.

The greatest gift the nation has given its people is the concept of non-violent protest or Satyagraha. Irom Sharmilla has been fasting unto death since a decade. Her goal is simply to request the government to reconsider the magnamity of its decisions. We backed Team Anna, Sharmilla needs our support too. Its not simply for a single state or for a single cause, its a backing for the people who feel alienated in their own country. Its against those narrow-minded people, who, in future might ask to separate yet another chunk of land. Its to reiterate the fact, once for all, that unity is probably our only protection against any malicious entity.