One of the interview questions asked to me was about driving 5 V inverter by a 3 V inverter.
LTSpice sims for the same: (.dc vgate 0 3 0.1)
Note that now the Vout is about 0.8V, PMOS is not fully off, and there's a current flow. If this Vout was to be the input of next stage, it would be interpreted by the gate as a 1 instead of a 0, and hence the need of level shifter logic.
Now if the load is C1//R, at equilibrium, current through cap =0, so final current through resi = Ic, Vout final = Ic*R. tau = RC
If load is L//R (choose a large L to see details in simulation because tau is L/R), Vout final = 0, Il exponentially increases 0 to final Il = Ic.
If load is only L, there is a voltage spike of Vout=Vdd at t=source connected to t = current stabilizes, and then Vout final =0, Il = Ic.
I= 1/L integr(Vdt)
Hence time taken for current to rise: t= IL/V = 0.4m*L
4. I was working on Ltspice and something very interesting happened. Now I am used to drawing transistors without substrate contact, but this model in Ltspice comes with substrate already tied. So inadvertently I tied substrate of PMOS (which is N type) to output instead of tying to Vdd. Now the reason we tie N substrate to Vdd is so that substrate - diffusion diode is reversed bias and off.
So Vin =0, expected inverter 1 output = high, substrate1 is high anyways and things seem normal.
inverter2: input high, PMOS is expected to be off, and output low. But note that there is a parasitic diode between N substrate, and P diffusion layers. The way this is set up, Source -> substrate diode is on, and substrate is connected to Drain. So we see Vout1= Vdd - diode drop.
My theory on why the same logic didnt apply for inverter1 is that current always follows a path of least resistance. I dont have handy values on me, but I guess channel resistance < diode resistance and hence current flew through channel, pulling output all the way to Vdd.
Vin = high, inverter1 output = Vdd - diode drop. What happens now is dependent on values of diode drop Vs Vthreshold. From the above simulation looks like PMOS was very mildly on in linear region, output nearly = Vdd - diode drop though it did bump up a little. (larger channel resi // diode resi, effective resi little less than diode resi and voltage bumped up a little).
Electronics is so interesting!
Note that now the Vout is about 0.8V, PMOS is not fully off, and there's a current flow. If this Vout was to be the input of next stage, it would be interpreted by the gate as a 1 instead of a 0, and hence the need of level shifter logic.
2. What would this synthesize to:
always @ (posedge clk or posedge rst)
begin
if (rst) y = 0;
begin
if (rst) y = 0;
else if (clk) y = d;
else y = y;
end
end
Xilinx ISE gave warning that: Clock and clock enable of register <y> are driven by the same logic. The clock enable is removed, and then synthesized it as regular flip flop.
So then how to make a latch out of it?
always @ (clk or rst)
begin
if (rst) y = 0;
else if (clk) y = d;
else y = y;
end
3. Constant Current source driving a capacitor: theoretically infinite voltage - lol!! well I had added capacitor voltage rating to my spice circuit, so to be honest I was disappointed that the spice diagram did not show white fumes coming out of the capacitor. Wouldn't it have been great if we could create infinite vtg..all power issues of the world solved in one stroke :p
Next, lets use Current mirror as constant current source instead of ideal current source. Cap charges to supply voltage of Current Mirror. And then C-B of Q2 forward biases, and Q2 isn't in Active region anymore.
Ic = (5-0.7)/2150 = 2 mA
Vout = Ic/C integr(t)
time to reach ~5V= 5 * 10^-7 / 2*10^-3 = 2.5*10^-4 = 0.25 ms
Vout = supply voltage doesnt solve any power issue of the world :) But definitely helps me understand things better. Thanks Aswin!
Next, lets use Current mirror as constant current source instead of ideal current source. Cap charges to supply voltage of Current Mirror. And then C-B of Q2 forward biases, and Q2 isn't in Active region anymore.
Ic = (5-0.7)/2150 = 2 mA
Vout = Ic/C integr(t)
time to reach ~5V= 5 * 10^-7 / 2*10^-3 = 2.5*10^-4 = 0.25 ms
Vout = supply voltage doesnt solve any power issue of the world :) But definitely helps me understand things better. Thanks Aswin!
Now if the load is C1//R, at equilibrium, current through cap =0, so final current through resi = Ic, Vout final = Ic*R. tau = RC
If load is L//R (choose a large L to see details in simulation because tau is L/R), Vout final = 0, Il exponentially increases 0 to final Il = Ic.
If load is only L, there is a voltage spike of Vout=Vdd at t=source connected to t = current stabilizes, and then Vout final =0, Il = Ic.
I= 1/L integr(Vdt)
Hence time taken for current to rise: t= IL/V = 0.4m*L
4. I was working on Ltspice and something very interesting happened. Now I am used to drawing transistors without substrate contact, but this model in Ltspice comes with substrate already tied. So inadvertently I tied substrate of PMOS (which is N type) to output instead of tying to Vdd. Now the reason we tie N substrate to Vdd is so that substrate - diffusion diode is reversed bias and off.
inverter2: input high, PMOS is expected to be off, and output low. But note that there is a parasitic diode between N substrate, and P diffusion layers. The way this is set up, Source -> substrate diode is on, and substrate is connected to Drain. So we see Vout1= Vdd - diode drop.
My theory on why the same logic didnt apply for inverter1 is that current always follows a path of least resistance. I dont have handy values on me, but I guess channel resistance < diode resistance and hence current flew through channel, pulling output all the way to Vdd.
Vin = high, inverter1 output = Vdd - diode drop. What happens now is dependent on values of diode drop Vs Vthreshold. From the above simulation looks like PMOS was very mildly on in linear region, output nearly = Vdd - diode drop though it did bump up a little. (larger channel resi // diode resi, effective resi little less than diode resi and voltage bumped up a little).
Electronics is so interesting!
